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Critical

Arm CPU TLBI completion permission bypass privilege escalation

IdentifiersCVE-2025-10263CWE-1223

CVE-2025-10263 is a critical Arm CPU erratum affecting multiple Arm cores, including C1-Ultra, C1-Premium, Neoverse V3/V3AE/V2/V1/N2/N1, Cortex-X925/X4/X3/X2/X1/X1C, and Cortex-A710/A78/A78AE/A78C/A77/A76/A76AE. The flaw arises from a timing/ordering condition during memory permission changes: completion of certain memory accesses is not guaranteed by completion of a TLBI, so a broadcast TLBI and subsequent DSB may complete before an overlapping store from another processing element is globally observed. As a result, software may still complete a write to a location that has just been changed from writable to non-writable. This can bypass Stage 1 translation, Stage 2 translation, or GPT protection and may permit writes into memory owned by a higher exception level.

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ANALYST BRIEF

Impact, mitigation & remediation

What it means. What to do now. Patch path, mitigations, and the assume-compromise checklist.

Impact

What an attacker gets, and what they’ve been doing with it.

Successful exploitation can allow privilege escalation by enabling writes after page-table or translation permissions have been changed to forbid writes. On affected systems this may let lower-privileged software write to resources owned by a higher exception level. In Xen on Arm, a malicious guest may be able to continue writing to memory after Xen revokes Stage 2 write permission, potentially escalating to hypervisor privilege. The issue affects integrity primarily; the provided material does not indicate read bypass, and Xen explicitly states reads are not affected.

Mitigation

If you can’t patch tonight, do this now.

No general mitigation short of applying vendor patches/workarounds is established in the provided material. Xen states there is no known mitigation besides patching. Operationally, exposure is limited to affected Arm systems, and in Xen deployments only multi-core Xen on Arm systems are affected; x86 is not affected. Reducing use of vulnerable systems in high-risk multi-tenant configurations until patched may reduce exposure, but this is not a vendor-stated workaround.

Remediation

Patch, then assume compromise.

Apply vendor fixes and software workarounds for affected platforms. Arm published a workaround for software performing TLB invalidation affecting Stage 1 or Stage 1+2 information that requires an additional TLBI and DSB. Use updated kernels/hypervisors incorporating this sequence. For Xen, apply the published XSA-493 patch sets for xen-unstable or supported stable branches (4.17 through 4.21 as provided by the advisory). For FreeBSD, upgrade to a corrected supported branch/version listed in FreeBSD-SA-26:31arm64 and reboot. Linux kernel patches implementing the mitigation were also reported as available.
PUBLIC EXPLOITS

Exploits

No public exploits tracked yet. Mallory keeps watching.

VALID 0 / 0 TOTALView more in app

No public exploit code observed for this vulnerability.

EXPOSURE SURFACE

Affected products & vendors

Products and vendors Mallory has correlated with this vulnerability. Open in Mallory to drill down to specific CPE configurations and version ranges.

VendorProductType
FreebsdFreebsdapplication
Microsoft CorporationWindowsoperating_system

Vendor-confirmed product mapping. Mallory continuously reconciles this list against your asset inventory.

What this page doesn’t show

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Exposure mapping

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Threat actor evidence

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Associated malware

Malware families riding this exploit, with evidence and IOCs.

Detection signatures

YARA, Sigma, Snort, and vendor rules, auto-deployed to your SIEM.

Vendor-by-vendor mapping

Cross-references every affected SKU, including bundled OEM variants.

Social activity11

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