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Nvidia announced its next-generation AI platform, Vera Rubin, during the CES 2026 keynote, introducing a rack-scale architecture designed to dramatically improve AI inference and training performance for data centers. The Rubin platform, which includes the Rubin GPU, Vera CPU, NVLink 6 switch, ConnectX-9 SuperNIC, BlueField-4 DPU, and Spectrum-6 Ethernet switch, promises up to 50 PFLOPS of inference performance per GPU and 288GB of HBM4 memory, delivering up to 5x greater inference performance and 10x lower cost per token compared to the previous Blackwell generation. Nvidia's CEO Jensen Huang emphasized the importance of "extreme co-design" across hardware and software to eliminate bottlenecks and reduce operational costs, positioning Rubin as a key enabler for scaling AI workloads across industries.
The Vera Rubin NVL72 rack is set to address the growing demand for AI compute in data centers, supporting advanced applications in robotics, autonomous vehicles, and large language models. Nvidia also highlighted its expanding open model portfolio for sectors such as healthcare, climate science, and robotics, and introduced the Alpamayo VLA model for autonomous driving, which will debut in the new Mercedes-Benz CLA. The Rubin platform is expected to be available in the second half of 2026, marking a significant leap in AI infrastructure capabilities and economic efficiency for enterprise and hyperscale deployments.
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Nvidia stated that the Vera Rubin NVL72 platform is expected to reach volume production in the second half of 2026. The production timeline accompanied the CES 2026 launch announcement and framed the platform's commercial availability.
Alongside the Rubin platform announcement, Nvidia introduced the Alpamayo vision-language-action model for autonomous vehicles, designed to interpret sensor data and make driving decisions. Nvidia said the new Mercedes-Benz CLA would be the first car to feature Alpamayo in the US later in 2026.
Nvidia said the Vera Rubin NVL72 rack would deliver up to 3.6 exaFLOPS of inference and 2.5 exaFLOPS of training performance per rack, while cutting AI token generation costs by up to 10x versus the prior Blackwell generation. The company also highlighted new memory and networking features, expanded trusted execution environments, and serviceability improvements such as modular design and zero-downtime maintenance.
At CES 2026, Nvidia CEO Jensen Huang introduced the next-generation Vera Rubin/Rubin AI data center platform, featuring the Vera CPU, Rubin GPU, NVLink 6, ConnectX-9 SuperNIC, BlueField-4 DPU, and Spectrum networking components. Nvidia positioned it as a rack-scale, tightly integrated AI infrastructure platform for training and inference workloads.
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Nvidia’s AI hardware business faced continued uncertainty in China as CEO **Jensen Huang** said Beijing had not yet approved imports of the **H200** GPU and confirmed that **no new H200 orders** were being placed while regulators decide. In parallel, Chinese GPU vendor **Shanghai Iluvatar CoreX** publicized a four-generation roadmap positioning its architectures (including *Tianshu* and successors) as domestic alternatives intended to compete with and ultimately surpass Nvidia’s Hopper/Blackwell and target Nvidia’s future **Rubin** platform by 2027, underscoring China’s push to reduce reliance on Western AI silicon. Outside the China licensing issue, Nvidia-related coverage also highlighted expansion and productization of AI compute: a report claimed Nvidia invested **$2B** in **CoreWeave** to support buildout of a planned **5GW “AI factory”** ecosystem by 2030 using multiple Nvidia platform generations (including **Rubin**, *Vera* CPUs, and *BlueField*). Separately, a review of *Nvidia DGX Spark* described a local AI development system built around the **GB10 Superchip**, reflecting growing demand for on-prem/local inference and development hardware as model sizes and VRAM requirements increase. Intel also outlined a separate, non-Nvidia event: a planned “hybrid” AI processor concept combining **x86 CPUs**, a fixed-function AI accelerator, and programmable logic for inference-focused workloads.
Jun 29, 2026
AI infrastructure demand is reshaping leading-edge semiconductor manufacturing economics and capacity planning. Reporting citing analysts and executive comments says **Nvidia** is on track to become **TSMC’s largest revenue customer**, driven by the high wafer and advanced packaging intensity of large AI accelerators versus smaller mobile/PC SoCs; one estimate projects Nvidia generating roughly **$33B** of TSMC revenue (about **22%** of total) versus Apple at **$27B** (about **18%**). The same demand dynamic is also stressing upstream constraints (power, wafers, and advanced packaging), with industry commentary pointing to rapid AI data-center buildouts and very large accelerator deployments as a key driver of the shift. In parallel, executives and reporting describe a broader push to expand manufacturing geographically as *capacity growth* rather than a wholesale relocation of Taiwan output. Nvidia CEO **Jensen Huang** publicly rejected claims that the U.S. aims to move 40% of Taiwan’s chipmaking to America, arguing new fabs in the U.S./Europe/Japan are needed because AI-driven wafer demand is outpacing what Taiwan’s infrastructure can support, while Taiwan remains central to the ecosystem; he also highlighted tight supply for **HBM and other memory** (HBM, DDR5, GDDR7, LPDDR5X, NAND) and coordination with **Samsung, SK hynix, and Micron** for next-gen accelerators (e.g., *Rubin*). Separately, **Samsung Foundry’s Taylor, Texas** site is reported to be approaching EUV “first light” and planning **2026 risk production**, including adoption of **EUV pellicles** and a large-scale ramp target, while **Intel** outlined a “hybrid” AI processor concept combining **x86**, a fixed-function AI accelerator, and programmable logic—signaling intensifying competition for AI inference workloads and continued pressure on advanced-node and packaging supply chains.
Jun 29, 2026
Huawei is advancing its domestic semiconductor ecosystem with the Ascend AI chip family, positioning its CloudMatrix 384 system as a direct alternative to Nvidia's GB200 platform. The Ascend 910C, a dual-chiplet accelerator with stacked HBM2E memory and DaVinci NPU architecture, is at the core of this effort, delivering up to 780 TFLOPS of dense BF16 compute. While the chip lags behind Nvidia's Hopper and Blackwell architectures in peak throughput and power efficiency, Huawei is compensating by scaling up deployments and building a robust supplier network, with over 60 semiconductor companies backed by its Hubble investment arm. This initiative is part of China's broader push for semiconductor independence, with local partners developing design toolchains and software ecosystems to reduce reliance on U.S. vendors. Meanwhile, AMD is preparing for the next generation of AI and HPC workloads by upstreaming Linux kernel patches for its upcoming Instinct MI400-series accelerators, likely based on the CDNA5 architecture. These patches indicate hardware enablement for new GPU IP blocks, including platform security and memory controllers, and suggest that AMD is moving forward with products intended to compete in the high-performance AI accelerator market. The developments from both Huawei and AMD highlight the intensifying global competition in AI hardware, with each company pursuing different strategies to address performance, efficiency, and supply chain independence.
Jun 29, 2026